When communicating information such as data content, memory addresses, and control bits from one integrated circuit or “chip” of an electronic device to another, it is necessary to ensure that each data buffer within the integrated circuit captures the transmitted data. In view of the trend for integrated circuits of electronic devices to process and transmit several hundred megabits per second or higher at faster rates, and because of delays and other impairments experienced by the signals carrying the data, it is becoming more difficult to synchronize a transmission of the data between the integrated circuits of the electronic device. With respect to memory devices such as a dynamic random access memory (DRAM), the problem can be exacerbated as a distance between data pins of the chips embodying the memory device (i.e., the memory chips) may be relatively long in comparison to other systems such as microprocessors.
A potential solution to the aforementioned limitation is to employ a different package design for the memory chips. Following the current packaging designs using bonding wires, pads for the memory chips are generally located in one or two rows of the package. Other systems embodied in integrated circuits such as microprocessors, as an example, are not limited in this aspect. The data pads may be located adjacent to one another with additional rows for the ground and virtual device driver pads surrounding the data bus on additional rows. Inasmuch as the above referenced packaging designs are significantly more expensive, however, the use of the designs is limited in a commodity market segment such as memory devices, especially when viable alternatives are available.
Another widely accepted alternative to synchronize the transmission of the data between the integrated circuits of an electronic device is to incorporate a clock recovery circuit therein. One approach incorporates a phase lock loop (PLL) into the clock recovery circuit to generate a PLL clock signal. The PLL clock signal is compared in phase to a system clock signal of the electronic device and the phase lock loop is adjusted until the two clock signals match. The use of appropriate filtering allows the PLL clock signal to match an “averaged” system clock signal (i.e., a clock signal wherein a random jitter has been filtered/averaged out). When the PLL clock signal and system clock signal are synchronized, a data latch of the respective integrated circuit of the electronic device can then transmit the received data for further processing within the electronic device. While the presently available clock recovery circuits including phase lock loops and other circuits have been adequate to date, the applications are becoming more limited in view of the higher quantity and rate at which the data is transmitted in the electronic device.
Looking at an architecture of a memory device, for instance, high speed data buses thereof frequently employ strobe signals to properly time a latching of the data associated with a data buffer of the integrated circuits of the memory device. As an example, a double data rate DRAM transmits strobe signals in phase with the data transmitted within the DRAM. The strobe signals typically employ the same drivers, data buffers and interfaces as the data in an attempt to synchronize the strobe signal to the data. Within the DRAM, the strobe signals are delayed to match a center of a data eye (e.g., 90 degrees, if the data is transmitted with both edges of a system clock) and then used as a clock to latch the received data. A system clock is usually employed to read out the data from a data latch of the respective integrated circuits of the DRAM and process the data therefrom.
To reduce a pin count associated with the memory chip, one strobe (or a differential strobe pair) is typically used for a multiple of data pins. With an increase in a frequency of the system clock, however, a distribution of the strobe signal to accommodate a delay between multiple data buffers in the memory device may be problematic. For instance, the integrated circuits of the memory device may experience timing complexities when the delay trends toward about half a bit cell. If a propagation delay of the clock signals across the data ports of the integrated circuits of the memory device approach a clock cycle time, implementation of balanced clock trees may be necessary for the strobe signal as well as for the system clock. In an attempt to maintain the strobe signals centered in a bit cell at a data buffer, the data bits may be delayed using dummy delays that model a strobe tree. The use of such additional circuits such as a balanced clock tree, however, adds to the complexity of the design of the memory device.
Accordingly, what is needed in the art is system and method for use with an electronic device that synchronizes a transmission of data therein in view of the escalating demands to transmit a higher quantity of data at a faster rate. More particularly, what is needed is a clock recovery circuit for an electronic device such as a memory device that latches the received data in synchronism with a system clock of the memory device that overcomes the deficiencies of the prior art.